Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The interconnects are usually formed by filling copper by a deposition process in features or cavities etched into the dielectric interlayers. Although Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD) techniques may also be used, the preferred method of copper deposition process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential interlayers can be electrically connected using vias or contacts.
In a typical process, first an insulating dielectric interlayer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches and vias in the insulating layer. Then, copper is electroplated to fill all the features. However, the plating process results in a thick copper layer on the substrate some of which need to be removed before the subsequent step. Conventionally, after the copper plating, CMP process is employed to planarize and then reduce the thickness of the copper layer down to the level of the surface of the barrier or insulation layer. In summary, CMP is used to remove all of the conductors from the surface so that copper-filled features electrically isolated from one another. However, CMP process is a costly and time-consuming process that reduces production efficiency. Further, more, although the CMP can be used with the conventional interlayer dielectrics, it may create problems with low-k dielectrics because of the mechanical force applied on the wafer surface during the CMP process. During the CMP step, the low-k materials may be stressed and may delaminate or other defects may form due to the low mechanical strength of the low-k materials.
Another material removal technique involves well-known electropolishing processes. In the electropolishing, which may also be referred to as “electrochemical etching” or “electroetching,” both the material to be removed and a conductive electrode are dipped into the electro-polishing solution. Typically an anodic (positive) voltage is applied to the material to be removed with respect to the conductive electrode. With the applied voltage, the material is electrochemically dissolved and removed from the wafer surface. However, this technology has a limited use in planarizing non-flat and non-uniform overburden copper layers because, during electroetching, material removal generally progresses in a conformal manner. Conformal nature of the process produces dishing defects in large features with small aspect ratios, which adversely affect wire dimensions.
This situation can be demonstrated with help of FIGS. 1A–1B. FIG. 1A illustrates a substrate 10 coated with a copper layer 12, having an overburden to be removed. The substrate is a preprocessed silicon wafer having an insulation layer 14 on top it. The insulation layer 14 is patterned and etched to form features 16, 18 such as trenches and field regions 20. FIG. 1A illustrates a narrow trench 16 with an aspect ratio of greater than 1 and a wide trench 18 with an aspect ratio of less than 1. By aspect ratio, it is meant a ratio of the depth of the trench to the width of the trench. Before the copper plating, the features 16, 18 and the field regions 20 are lined with a barrier layer 22 (such as Ta/TaN) and a copper seed layer (not shown). Conventional electrodeposition processes may fill the narrow features 16 in a bottom-up fashion by utilizing additives in electroplating baths and thus yield a flat surface as shown in FIG. 1A. However, copper deposits conformally over the large features 18 and produces recess 23 over such features. As mentioned above, electroetching of the copper layer 12 also progresses conformally during the standard electroetching process. As shown in FIG. 1A, as the etching of the copper layer progresses, the top surface 24 of the copper layer 12 gradually approaches the features 16, 18. This situation is shown by dotted lines 24′, 24″ and 24′″. When the etched surface 24′″ is reached, some copper is still on the field regions but the copper in large feature is over etched. As shown in FIG. 1B, as the remaining copper on the field regions is etched away, copper in the large feature 18 is dished because of excessive removal. The large feature in this example may be a trench with a width larger than 10 micrometers.
Dishing problems originating from the conformal nature of the electroetching process may be alleviated by utilizing methods that partially planarize the overburden layer employing, for example, CMP or another planarization technique prior to the electroetching step. In such approaches, once the overburden is made flat, resulting flat surface is uniformly etched back down to the barrier layer. However, such multi-process approaches are cumbersome and time consuming. Besides, success of such processes strictly depends on the thickness uniformity of the flat layer that the electroetching process is initiated on. If the flat copper layer has slight local or global thickness non-uniformities, i.e., thinner and thicker areas, the features under the thinner copper layer are most likely dished while the thicker copper layer is still being removed from other thicker areas on the wafer. Such thickness non-uniformities can be the result of various reasons such as copper plating tool design, plating chemistry problems, problems with electrical contact to the wafer, plating solution problems, and the like. Alternately, there may be non-uniformities in the electro etching process itself that may cause non-uniform material removal from various parts of the substrate.
FIG. 2A illustrates a region of a substrate 30 having a copper layer 32 that is partially planarized and has thickness non-uniformity, which is exaggerated to clarify the point. In this example, t1 is the measured thickness taken near a first feature 34 and t2 is the measured thickness taken near a second feature 36. If t1 is greater than t2, as shown in FIG. 2B, the copper in the second feature 36 will be dished while the copper over the first feature 34 is planarized and leveled with the barrier layer 38. FIG. 2C shows another area on the substrate 30 where copper layer 32 is thinner with measured thickness t3 near a third feature 40, but it is thicker with measured thickness t4 near a fourth feature 42. As shown in FIG. 2D, in this case, removal of thin copper layer on the third feature is faster than the removal of the copper layer on the fourth feature 42. As a result, as the fourth feature 42 is planarized down to the level of barrier layer 38, the third feature 40 is dished. As described above, due to the thickness non-uniformities of the copper layer, conventional electroetching processes either over etch the copper in all of the features or over etch it in some of features while planarizing it in some features. A process that slows down or stops etching of the areas that begins to dish but accelerates etching of the un-etched areas would overcome above drawbacks.
Certain variations of electroetching process attempt to alleviate such process drawbacks. In one technique, for example, such recesses are filled or masked with a low ionic conductivity and low diffusivity material before the wafer is placed into the electroetching system. Use of such material coating on the wafer surface is claimed to slow down the etching of such recess areas during electroetching, and planarize the copper film.
To this end, however, there is need for alternative etching techniques that etch back even highly non-uniform conductive films with greater efficiency and those that do not cause excessive dishing into the features.